Wafer Level Testing on NI STS


Multi-Site Wafer Testing on NI STS


Semiconductor devices are manufactured on a wafer, a round piece of silicon that resembles a  compact disk in appearance. For very small devices such as LNAs (Low Noise Amplifiers) there can be over 100 thousand devices on a single wafer.

This huge number, combined with the incredibly small size of the actual device, makes testing while still on the wafer very difficult. This “wafer level testing” is however a very important part of production, as it is the first time the “finished” device is tested. Catching failed devices at this stage prevents them from incurring the costs of being packaged, only to then fail the final testing process.

For a detailed description of the semiconductor manufacturing process, including the test steps, see this article from Wikipedia

The Semiconductor Test System from National Instruments (NI STS) is a PXI based system specifically developed for the semiconductor industry. When combined with a handler/prober is offers industry standard high volume wafer level testing

The NI STS is controlled by a combination of LabVIEW and TestStand, with the test sequences being implemented using an add-on called the TestStand Semiconductor Module (TSM). The TSM module allows the use of familiar tools when configuring tests, such as Pin Maps and Binning.


When a NI STS is purchased it is “blank” from a users perspective, the only software installed is the platform services (LabVIEW, TestStand and TSM). Before the STS can be used, the test sequence needs to be developed, approved and released.

At our customer site this development fell onto the Test Engineering department, a group of engineers who are specialists in developing tests and analysing results. While some have experience in using LabVIEW, they are not specifically “LabVIEW developers”, they are more used to the “old iron” ATEs from companies such as Advantest and Teradyne.

In order for our customer to get the most out of the NI STS they needed a solution that allowed quick and easy development of test sequences, as well as a familiar interface that allows standard practices to be applied.

As this was the first product to be tested using the NI STS one additional task was to see if using it offered better efficiency that their current pool of testers. This includes sequence development time, sequence validation, total test time and reliability.


For our customer we developed a process of developing a test sequence that required limited knowledge of LabVIEW and TestStand, making it simple for the test engineers to use without specialist training. 

The first step was to use LabVIEW to develop the individual tests, this allowed us to have the flexibility to test the hardware as well as find optimal architecture for the software. Each test was developed, debugged and optimised in a lab environment to avoid unnecessary time in the actual test area (this was a clean room environment and wasn’t the most comfortable place to work!)

During this development we asked other departments to analyse some of the data – using various statistical methods – and also held code reviews to both check for mistakes and explain the operation. This proved quite interesting as there were often 2 or 3 ways of doing the same test, with different people arguing for each method.

As the STS hardware and the TSM software were relatively new products, we were in constant close contact with NI regarding issues, bugs and potential improvements. Between ourselves, NI and our customer we successfully implemented a test sequence that enabled multisite testing of LNAs and dramatically reduced the total test time for the whole wafer. 

This project really was a team effort, between experts in different areas all pooling their knowledge to get the job done. It really was a privilege to be part of this project, what we achieved together was no small feat.

This project is part of our Semiconductor division